The invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a trench gate structure and a method of manufacturing the same.
Semiconductor devices such as trench gate MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are used in various applications including electric power switching. For example, a trench gate MOSFET of a small size is used as a fast switching component having an operating frequency of about 500 kHz for stepping down the supply voltage inside a personal computer (e.g., 17 volts) to a power level for its CPU or various disk drives (e.g., 1.7 volts).
Recent demands for energy saving require these semiconductor devices to have higher efficiency. To this end, it is effective to reduce conduction loss or “on-resistance (Ron)” of the components. To achieve this, reduction of on-resistance has been attempted by downscaling of cells. In particular, significantly high density can be achieved by using a “trench gate structure” for the component structure to gain the channel width.
To improve the operating efficiency of trench gate semiconductor devices, reduction of its switching loss (Qsw) as well as reduction of its “on-resistance” is required. To reduce the switching loss, it is important to reduce “parasite capacitance” of the component to increase its operating rate. The parasite capacitance of the component may include the drain-gate capacitance (Cgd), drain-source capacitance (Cds), and gate-source capacitance (Cgs). Among these capacitance components, reduction of the drain-gate capacitance (Cgd) is particularly effective for reducing the overall capacitance.
In this respect, a structure is disclosed which can decrease Cgd by increasing the thickness of gate oxide film at the bottom of the trench (see, e.g., Japanese Patent No. 2647884).
FIG. 23 is a schematic cross-sectional view showing a structure in which the gate oxide film has an increased thickness at the bottom of the trench as described above. More specifically, it has a trench that penetrates a p-type base region 5 and extends to an n-type epitaxial region 6. A gate oxide film 3 is formed on the inner wall of the trench, and a gate electrode 1 fills the remaining space of the trench. The gate oxide film 3 comprises a gate oxide film 3a having smaller film thickness, and a gate oxide film 3b having larger film thickness.
The boundary between the p-type base region 5 and the n-type epitaxial region 6 is denoted by B1, and the boundary between the thin gate oxide film 3a and the thick gate oxide film 3b is denoted by B2. Downward shift of the boundary B1 relative to the boundary B2 leads to insufficient formation of the channel region by the gate voltage, which causes a problem of increased on-resistance (Ron). On the other hand, upward shift of the boundary B1 relative to the boundary B2 causes a problem of increased drain-gate capacitance (Cgd). That is, in this structure, ideally, it is preferred to align the boundary B1 with the boundary B2.
In practice, however, it is very difficult to always align the boundary B1 with the boundary B2. This is because the p-type base region 5 is formed by diffusion of p-type impurities into the surface of the epitaxial layer, which causes certain variations in its formation depth. On the other hand, certain variations for the depth of the trench are also unavoidable because the depth is controlled by the process time for etching such as RIE (reactive ion etching).
It is therefore difficult to reproducibly achieve an ideal positional relationship of aligned boundaries B1 and B2 irrespective of whether the top of the trench (or the surface of the base region 5) or the bottom of the trench is taken as a reference. For this reason, according to the conventional art, it has been difficult to stably obtain a structure of a trench gate semiconductor device in which low on-resistance (Ron) and low switching loss (Qsw) are simultaneously achieved.